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　　三維集(ji)(ji)成(cheng)(cheng)(cheng)是通過(guo)在(zai)垂直(zhi)方(fang)向上將多個(ge)獨立的(de)(de)芯(xin)(xin)片(pian)或功能層(ceng)堆疊在(zai)一起的(de)(de)器(qi)(qi)件(jian)系統，能夠實現(xian)邏輯、存儲和(he)傳感等功能的(de)(de)垂直(zhi)集(ji)(ji)成(cheng)(cheng)(cheng)和(he)協同(tong)工(gong)作(zuo)，是后摩爾時代的(de)(de)重(zhong)要技術路線(xian)。目前(qian)商用的(de)(de)三維集(ji)(ji)成(cheng)(cheng)(cheng)主(zhu)要是通過(guo)封裝技術將多芯(xin)(xin)片(pian)或者多芯(xin)(xin)粒垂直(zhi)堆疊和(he)互聯(lian)。單(dan)芯(xin)(xin)片(pian)三維集(ji)(ji)成(cheng)(cheng)(cheng)則是直(zhi)接(jie)在(zai)同(tong)一芯(xin)(xin)片(pian)內部垂直(zhi)集(ji)(ji)成(cheng)(cheng)(cheng)多個(ge)器(qi)(qi)件(jian)層(ceng)。通過(guo)將每一器(qi)(qi)件(jian)層(ceng)直(zhi)接(jie)制備在(zai)另一器(qi)(qi)件(jian)層(ceng)之上，能夠進一步(bu)提(ti)高芯(xin)(xin)片(pian)的(de)(de)互聯(lian)密度和(he)性(xing)能。然而，硅基(ji)單(dan)芯(xin)(xin)片(pian)三維集(ji)(ji)成(cheng)(cheng)(cheng)面(mian)臨著嚴重(zhong)的(de)(de)熱(re)預算問題，其上層(ceng)的(de)(de)硅溝道制備工(gong)藝會導致下(xia)層(ceng)硅器(qi)(qi)件(jian)摻雜(za)擴散(san)和(he)性(xing)能退(tui)化，限制了(le)三維集(ji)(ji)成(cheng)(cheng)(cheng)的(de)(de)發展。

　　針對這一(yi)挑戰，湖南大學(xue)物理與(yu)微電(dian)(dian)子科學(xue)學(xue)院劉淵教授團(tuan)隊報道(dao)了(le)一(yi)種低(di)(di)(di)溫的(de)(de)范(fan)德華(hua)單芯片(pian)三維集(ji)成工藝(yi)。在該工藝(yi)中，源/漏(lou)/柵電(dian)(dian)極、層(ceng)(ceng)(ceng)內互(hu)連(lian)金屬、高κ柵介(jie)電(dian)(dian)質、低(di)(di)(di)κ層(ceng)(ceng)(ceng)間介(jie)電(dian)(dian)層(ceng)(ceng)(ceng)和層(ceng)(ceng)(ceng)間垂(chui)直通(tong)孔等電(dian)(dian)路(lu)功(gong)能(neng)層(ceng)(ceng)(ceng)首先(xian)預(yu)制備在犧牲(sheng)晶圓上，之(zhi)后在120 °C的(de)(de)低(di)(di)(di)溫下范(fan)德華(hua)集(ji)成到半導(dao)(dao)體晶圓上。通(tong)過(guo)逐層(ceng)(ceng)(ceng)集(ji)成范(fan)德華(hua)預(yu)制備電(dian)(dian)路(lu)層(ceng)(ceng)(ceng)和半導(dao)(dao)體層(ceng)(ceng)(ceng)，團(tuan)隊實現(xian)了(le)10層(ceng)(ceng)(ceng)的(de)(de)全范(fan)德華(hua)單芯片(pian)三維系統。同(tong)(tong)時，團(tuan)隊發(fa)現(xian)范(fan)德華(hua)集(ji)成工藝(yi)不會對底部的(de)(de)硫化(hua)鉬晶體管電(dian)(dian)學(xue)性能(neng)產生影響(xiang)，能(neng)夠保證晶體管的(de)(de)本征性能(neng)。進一(yi)步集(ji)成不同(tong)(tong)功(gong)能(neng)的(de)(de)電(dian)(dian)路(lu)層(ceng)(ceng)(ceng)，團(tuan)隊實現(xian)了(le)邏(luo)輯(ji)、傳感(gan)和存儲互(hu)聯的(de)(de)三維異質集(ji)成和協(xie)同(tong)(tong)工作。該研究(jiu)為單芯片(pian)三維集(ji)成系統提(ti)供(gong)了(le)一(yi)條(tiao)低(di)(di)(di)能(neng)量路(lu)徑。

　　5月22日(ri)，該研究成(cheng)(cheng)果以“Monolithic three-dimensional tier-by-tier integration via van der Waals lamination”為(wei)(wei)題在線發表在《自(zi)(zi)然(ran)(ran)》雜(za)志上，湖南大學為(wei)(wei)獨立完成(cheng)(cheng)單位，作者(zhe)分(fen)別來(lai)自(zi)(zi)物電(dian)院(yuan)、化工院(yuan)、半導體學院(yuan)。物電(dian)院(yuan)陸冬(dong)林博士為(wei)(wei)第一(yi)作者(zhe)，物電(dian)院(yuan)劉淵(yuan)教(jiao)授為(wei)(wei)唯一(yi)通訊(xun)作者(zhe)。該工作得到了來(lai)自(zi)(zi)國家自(zi)(zi)然(ran)(ran)科學基金、國家重點研發計劃等項(xiang)目的資助。

　　論文鏈接：//www.nature.com/articles/s41586-024-07406-z